In SerDes applications, or any application requiring a low noise (low jitter) master clock of very high frequency, it is usual to require synchronism with a common, distributed, high stability reference clock of much lower frequency. To do this, a VCO and other elements needed to form a PLL are used. However, the reference clock only regulates frequency and jitter in a frequency band much lower than the reference frequency, so the VCO must be responsible for the noise and jitter at all higher frequencies up to the master clock frequency. The type of VCO with lowest noise that is readily available in integrated circuit environments is an LC type, based on the resonance of a capacitor in parallel with an inductor, both of which can be built with relatively high quality (Q) factors, i.e., low energy loss per cycle, using standard available circuit layers. However, the inductor is a relatively large conductor loop which forms an effective antenna that is relatively sensitive to electric and particularly to magnetic fields from any source, particularly nearby electrical circuits. Since the LC circuit is designed to achieve a high Q factor to minimize noise by minimizing bandwidth, the circuit is primarily sensitive to frequencies centered on the LC resonant frequency and lying within the bandwidth of the VCO circuit, which is typically no more than about 0.05% of the resonant frequency. Hence, the best means of avoiding interference is to use a resonant frequency that is not near to any of the primary or secondary frequencies used or produced by nearby circuitry. Because the purpose of the VCO is to provide the clocks for all such nearby circuitry, this means some method of shifting the VCO frequency by some non-trivial factor must be used, and in particular an integer factor such as 2 or ½ must not be used. Rather, a factor of 1.5, 1.2, or even better 0.8 is best to avoid all significant harmonics and sub-harmonics. A relatively low frequency is desirable because generally at high resonant frequencies Q falls with frequency while power increases. For similar reasons, even the master clock does not operate at the full bit-rate; rather, it operates at ½ bit-rate so that each half-period defines one bit-period, and every clock edge is fully and equally used.